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gEDA-user: Bug in fab drawing

To: geda-user@seul.org
Subject: gEDA-user: Bug in fab drawing
From: Mark Rages <markrages@mlug.missouri.edu>
Date: Thu, 7 Oct 2004 12:23:49 -0500
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My board has both plated and unplated 0.065 holes.

In both postscript and gerber output, the drill list on the fab drawing 
has the plated and unplated hole descriptions overlapping.

Here is an example output:
http://mlug.missouri.edu/~markrages/fab.ps

I'm using pcb-20040903 with the "mode button patch".

Regards,
Mark
markrages@mlug.missouri.edu

PS. I sent my design to Advanced Circuits yesterday... wish me luck!

-- 
You think that it is a secret, but it never has been one.

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