Re: gEDA-user: QFP fan-out tips

[Ian Chapman <ichapman@xxxxxxxxxxxx>]

EMC and vias.  Last I was told it was 0.7-nH per via.  Total inductance
rule of thumb, from start to end of trace is approx 10-nH per cm plus
0.7-nH per via.  Of course shorter via the better (thin pcb) but the dia
will not make too much difference however the more surface area the
better.  To reduce the inductance use short traces and the above rule
can be divided by 3 or so if the trace width is 1/3 of length.  Not to
practical in many cases.

	Via under pad I have not used or seen, but there is a smt process for
that: you need to go over the rules for that with the PCB manufacturer
and assembler.

	Once I was an EMC expert.  Regards Ian.



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