Re: gEDA-user: Ground Flooding

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Fri, 2008-10-03 at 13:16 +0100, Peter Clifton wrote:
> On Thu, 2008-10-02 at 23:59 +0100, Peter Clifton wrote:
> > On Thu, 2008-10-02 at 14:48 -0700, Kingston Co. wrote:
> > 
> > > Also, you can fix this by editing your *.pcb file manually and adding
> > > the "clearline" flag to all your lines.
> 
> URG... I'd not noticed that before. Every single line in the design has
> to have "clearline" added. Sounds like hindsight would put the
> "polarity" of this flag the opposite way around, but never mind.

And just to make this more confusing to those who are reading the source
code, as far as I can tell, the "join" flag does't exist.

ClrFlag(Selected,Join) actually _sets_ (not clears) the "clearline" flag
on that line. I guess the ClrFlag is just an abstracts to what seems the
more logical expression of this functioanlity.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)



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