Re: gEDA-user: Logic simulation

[Tuukka Toivonen <tuukkat@ees2.oulu.fi>]

On Thu, 6 Sep 2001, Ales Hvezda wrote:

> >With Electric editor (www.staticfreesoft.com) you can enter your
> >circuit schematics graphically and export as IRSIM simulation deck file.
> 	Hmmm... what does electric import wrt this internal simulator?

Simple structural VHDL, I suppose. There's also bunch of other supported
formats, such as CIF, GDS, and others, but unless they contain connection
information they mightn't work with the simulator.

> 	Yeah, that might be of interested.  Anybody have any docs on
> what IRSIM decks look like?

The man page comes with Magic layout editor, it's easy to find from the
net or look here: http://www.ee.oulu.fi/~tuukkat/tmp/man_sim.html.

Just to give you a feeling what Electric does, there's a piece of
automatically generated VHDL (from a schematic) that can be
directly used with the Electric internal simulator:

-- VHDL automatically generated from facet xxx{sch}
entity xxx is port(a, b, c, d: in BIT; y: out BIT);
  end xxx;
architecture xxx_BODY of xxx is
  component xor2 port(a1, a2: in BIT; y: out BIT);
    end component;
  component nand2 port(a1, a2: in BIT; y: out BIT);
    end component;
  component nor2 port(a1, a2: in BIT; y: out BIT);
    end component;
  signal NET47, NET46: BIT;
begin
  node6: xor2 port map(NET46, NET47, y);
  node7: nand2 port map(b, a, NET47);
  node8: nor2 port map(d, c, NET46);
end xxx_BODY;