gEDA-user: Re: IVL error?

["CN" <mis4@xxxxxxxxxxx>]

[I am posting this msg orginally posted to the -dev, here also.]


I have a self standing test below show the problem. Just 'iverilog this_file'.


========

module test;

dff d1 (.Q(qq), .C(clk), .D(dd));

reg dd, clk;

initial begin dd =0; clk=0; end

endmodule


primitive dff (Q, C, D, notifier);

output Q;

reg Q;

input C, D, notifier;

table

// C D notifier : Q : Q+ 

(01) 0 ? : ? : 0 ; //normal clocking case

(01) 1 ? : ? : 1 ; //normal clocking case

(01) x ? : ? : x ; //normal clocking, input undefined

(b0) ? ? : ? : - ; //clock falling or held low

// if the above is changed to the following, it goes thru

// (10) ? ? : ? : - ; //clock falling

// but the following, which (b0) should iterate to fails also

// (00) ? ? : ? : - ; //clock held low


b (??) ? : ? : - ; //hold Q if D changes

? ? * : ? : x ; //notifier case

endtable

endprimitive

======


--Original Message Text---

From: CN

Date: Wed, 31 Aug 2005 17:21:14 -0700


Hi,

I am using the 0.8.x branch from CVS.


I have many primitives like the following in my sim library.


==========

primitive dff (Q, C, D, notifier);


output Q;

reg Q;

input C, D, notifier;


table

// C D notifier : Q : Q+ 

(01) 0 ? : ? : 0 ; //normal clocking case

(01) 1 ? : ? : 1 ; //normal clocking case

(01) x ? : ? : x ; //normal clocking, input undefined

(b0) ? ? : ? : - ; //clock falling or held low <<<<<

b (??) ? : ? : - ; //hold Q if D changes

? ? * : ? : x ; //notifier case

endtable

endprimitive

=========


ivl gives a parse error on the line marked <<<<< above (ModelSim accepts it). It seems the (b0) gives a conflict because ivl does not accept (00). If I change this to (10) it will go thru.


Has anybody seen this problem? Has this been fixed in the later versions?


Cordially, CN