Re: gEDA-user: a pcb level panelizer tool

[John Griessen <john@xxxxxxxxxxxxxx>]

DJ Delorie wrote:

>> What would it take to update a netlist from a layout change?
> 
> That's the general "back annotation" problem we've talked about
> before.  In this case, it would be the wrong thing to do - you start
> with one U14, you create a *second* U14, *then* renumber *one* of them
> to U24.  Which schematic do you update?

Yes, sorry, I was musing confusedly.  A netlist from layout would best 
ignore any layout connections, and only be concerned with refdes's and 
BOM lists.

Updating a flat schematic would be tricky AI or next to useless...layout 
driven schematics doesn't have a good ring to it...  Who would want it?

Once you have the netlists matching, you want back annotation of attribs 
only, which is a different idea.  Nevermind...


> 
> I think a better long-term goal here is to add heirarchical PCBs, and
> match them to the heirarchical schematics.  Then you could lay out one
> exemplar block and instantiate it once for each module.

Nirvana-like!  Yes, that's the goal we want to set.

John Griessen


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