Re: gEDA-user: Fwd: Re: [OH Updates] How can you help solve the proprietary tool problem?

[Andy Fierman <andyfierman@xxxxxxxxxxxxxxx>]

> - back-annotation to schematic from the PCB editor.

An example of where this is essential is if impedance controlled nets
end up having to cross plane breaks and extra capacitors have to be
added to couple the ground return paths between the planes.

A net in the schematic may have an impedance constraint on it. When it
is passed into layout, the net then ends up having to cross from over
a ground plane to over a power plane. Capacitors may have to be added
to bring the ground return path close to the plane crossing point.
Other than by adding a number of redundant capacitors to the
schematic, there is no way the need for these extra capacitors can be
predicted from the schematic so they have to be added to the layout
and then back-annotated into the schematic.

I know this is bad practice but there are often situations where
physical constraints on layer count such as dimensions or costs mean
that the layout is limited to a certain number of layers.

Cheers,

         Andy.

signality.co.uk




2011/9/3 Steven Michalske <smichalske@xxxxxxxxx>:
>
>
>
>
>
> On Sep 2, 2011, at 12:45 PM, Colin D Bennett <colin@xxxxxxxxxxx> wrote:
>
>> On Fri, 02 Sep 2011 10:18:20 -0500
>> John Griessen <john@xxxxxxxxxxxxxx> wrote:
>>
>>> Does the category low end bother you?
>>
>> Well, I think low-end is not very specific in reality.  Does gEDA
>> really belong in the category of EAGLE, or is it much more powerful?
>>
>> Maybe the “low-end” attitude toward gEDA is based on the fact that pcb
>> doesn't support important features for large and complex boards such as
>>
>> - trace length matching,
>
> Important in high speed.
>
> I recall a serpentine plugin for pcb.
> +1 to bundling plugins with pcb sources......
>
>> - constraints/routing styles defined at the net level,
>
> Important for high speed and power applications
>> - pushing/pulling PCB traces and better support for moving parts with
>>  traces routed,
> Nifty, aids layout but often you can't shove those length matched sets anyhow.....
>
>> - ability to select a component on the PCB by clicking it in the
>>  schematic view,
> Novice feature....  Layout engineers have paper schematics with notes taken on them when they met with the EEs who drew the schematics.
>
>
>> - back-annotation to schematic from the PCB editor.
> Again,  back annotation comes from yelling at the EE and telling them that they can't break physics no mater how hard they try!
>
> On the other hand for FPGAs and other high pin count devices I suspect that this would be more welcome.  Though I think that a tool that mapped the ports and I/Os an stored them in a table.  With an option to render to graphical symbols would be better.
>
> Nets in schematic assigned to layout placement. Then layout is assisted by assignment tool, kinda like a reverse fanout tool.  Then The table in the design is updated.  Then graphics and pinmap file get generated.
>
> This would cut the iterative process from the desiring of large FPGA parts.
>
>>
>> Just a few things that sound important to me, a novice PCB designer.
>
> What is really missing is the support contracts from the high end tools.  We need the equivalent of what RedHat is for Linux to be considered a high end tool.
>>
>> Regards,
>> Colin
>>
>>
>> _______________________________________________
>> geda-user mailing list
>> geda-user@xxxxxxxxxxxxxx
>> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
>
>
> _______________________________________________
> geda-user mailing list
> geda-user@xxxxxxxxxxxxxx
> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
>


_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user