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Re: [school-discuss] Spreading LTSP over multiple servers?

On Tue, 02 Dec 2003 10:25:37 -0700
Harry McGregor <micros@osef.org> wrote:

Harry> Modern chipsets/cpus (as the L2 has moved onto the CPU) have a cacheable
Harry> memory region that is as large as their memory address space.  Thus the
Harry> two cpus in this system, each with 256KB L2 and 128KB of L1 of cache,
Harry> are able to fully cache the entire 3GB of ram, as needed.

Hey, thanks for this accurate explanation :-)