[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

Re: [f-cpu] fadder forever

gaetan@xeberon.net a écrit :

Not necessary to calculate the difference both ways. Remember that
CSAdd is a compound adder. You get `Ea - Eb' at the incremented output
and `not (Eb - Ea)' at the normal output. Thus, calculating `Eb - Ea'
requires only a single row of inverters, not a complete second adder.

yes, that's true... it add a 1-gate delay
it causes a little problem in stage 3:
i had a 4-bit shifter (a shifter that can shift a vector following an other 'driver' 4bit-vector, so
which can shift by 0 to 2^4 positions). So d=4, t=4
So i had a conditional bit inverter (d=2) and it fitted into the stage.
But now i have a 5 bit adder, so there is not enough space to put the inverter...
do i have the right to violate the 6-gate delay?
i have 2 solutions i don't know how to balance:
- I can put the whole conditionnal inverter in the 4th stage, - or i can precompute the inverted vector in the 3th stage (so i need an additional register vector).

in fact it doesn't cause this problem since the xor in now in the first stage, but i would like to know how to balance between area/latency anyway.

arggg... synthesis is much harder than i expected....


~~ Gaetan ~~

To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu in the body. http://f-cpu.seul.org/