```hi !

gaetan@xeberon.net wrote:

```
```gaetan@xeberon.net a écrit :

```
Not necessary to calculate the difference both ways. Remember that
CSAdd is a compound adder. You get `Ea - Eb' at the incremented output
and `not (Eb - Ea)' at the normal output. Thus, calculating `Eb - Ea'
requires only a single row of inverters, not a complete second adder.
yes, that's true... it add a 1-gate delay
it causes a little problem in stage 3:
i had a 4-bit shifter (a shifter that can shift a vector following an other 'driver' 4bit-vector, so
which can shift by 0 to 2^4 positions). So d=4, t=4
So i had a conditional bit inverter (d=2) and it fitted into the stage.
But now i have a 5 bit adder, so there is not enough space to put the inverter...
do i have the right to violate the 6-gate delay?
i have 2 solutions i don't know how to balance:
- I can put the whole conditionnal inverter in the 4th stage, - or i can precompute the inverted vector in the 3th stage (so i need an additional register vector).
hum...
in fact it doesn't cause this problem since the xor in now in the first stage, but i would like to know how to balance between area/latency anyway.
thx

arggg... synthesis is much harder than i expected....
```
don't worry too much about inverters.
additional trransistors. Take, for example, LUT-based FPGAs :
you can get whatever value you want for a mostly constant "cost"
(but a slightly higher unit cost).
For cell-based ASIC, NAND takes less transistors than AND,
which is a NAND followed by a NOT.
Since CMOS is today's dominant technology, it's not much
a problem.
Same for memory cells that are based on flip-flops :
the data is "latched" by two inverters (or other gates)
back to back, so you (could) have both inverted and non-inverted

Ok, these are some "hints" and "heuristics" for the design.
There are many more, i just wanted to remove some pressure
on this subject and i probably involuntarily transfered the
pressure on something else, excuses in advance.

I'm still investigating on the FPGA issue,