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Re: [f-cpu] "A structured VHDL design method"

Le Mardi 24 Février 2004 00:53, Michael Riepe a écrit :
> On Mon, Feb 23, 2004 at 05:08:16PM +0100, nico@seul.org wrote:
> [...]
> > The main practice is to use records and 2 processes by entites (one
> > combinational and one synchronous). The goal is maintenability. A must
> > read !
> Do you really think it's a good idea to put the "stuff" from 5 or 6
> uge pipeline stages into a single process?  I don't.

i don't too :)

In fact it use 1 entites for each stage. If you want 1 entites, you could have 
the 2 process for each stages, but i beleive that you could use explicit name 
for register of the pipeline. It's a question of size i think. Look at the 
exemple where it instanciate the pipeline of the cpu.

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