Re: gEDA-user: Driving the netlist from PCB (instead of gschem)

[Rick Collins <erudite999@xxxxxxxxx>]

At 01:44 AM 9/28/2008, you wrote:
>Projects with microcontrollers and FPGAs often have a lot of flexibility
>in how things get connected.  My workflow for those projects is to build
>a sparsely connected schematic and then move to PCB to explore geometry
>options.  Once I see what will be easy to route in PCB I start making
>connections based on the physical layout.  Sometimes I do this by picking
>a starting pin and assigning them sequentially in gschem (FPGAs make this
>fairly easy, at least with "linear" packages).  Sometimes I use 'D' and
>'Shift-D' to annotate pins or bring up the whole package in PCB so I know
>which pins I can consider and then just route them (with auto-DRC disabled,
>kind of a bummer) and use the conflicts to back-annotate the PCB.
>
>I'd really like to be able to do a couple of things more easily:
>
>1.  I'd like be able to express the design requirements in gschem and
>have them visible in PCB.  For example, I'd like to say "connect this
>SRAM address bus to this bank of FPGA pins... somehow" and see that in
>PCB.  Some kind of "meta rat" that would help me see both the geometry
>and the pins that are in play.
>
>2.  I'd like to be able to resolve these dependencies (even in the absence
>of 1, as today) by drawing lines in PCB and having the info get back to
>gschem automatically.  Perhaps by adding a wire+netlist attribute+busripper
>at the appropriate pin.
>
>Does anyone know if/how good commercial tools do this?
>
>Any ideas for how to express a "meta rat"?  How to visualize it?  How to
>specify it in gschem, in a netlist, etc?
>
>Any better ideas for how a line drawn in PCB could be automatically driven
>back to a schematic?  Perhaps as a "rat" in gschem??


Personally, I have never found the use of back-annotation to be very 
user friendly.  I prefer to open both tools at once and make the same 
changes in both tools at the same time.  When I see I want to swap 
pins in the layout, I do that in the layout tool and also in the 
schematic tool.  At some point I re-import the netlist and verify 
that the two tools still agree on connectivity.

The idea of a rat line in a schematic tool is interesting.  But it 
could be difficult to implement without ripping up the entire drawn 
net.  I guess the drawn net could be left intact and the final 
connection could be removed at the pin that is no longer in the 
net.  If that is at the FPGA end, it could work fairly well.

Personally, I favor the idea of a unified data base for both layout 
and schematic.  So far no one seems to agree with this idea.  I 
recently found out that IPC has a standard file format for layout 
information.  This is new and it is not clear if it includes 
schematic info.  But it does include a lot of fabrication oriented 
info.  If a common format for all phases of the design process could 
be adopted, things like this can be handled without generating 
intermediate files.

Rick 



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