Re: [f-cpu] Simulator

[nicO <nicolas.boulay@ifrance.com>]

Yann Guidon a écrit :
> 
> hi,
> 
> Ben Franchuk wrote:
> > Michael Riepe wrote:
> >
> > > That's the other side of the medal.  IMHO, we need both a cycle-accurate
> > > simulator and an instruction-level emulator.  The former will be used
> > > for studying, debugging and improving the design, the latter supports
> > > early software development, and it probably also helps cleaning up the
> > > instruction set, clarifying open ends and so on.
> >
> > Are their any tools to keep things in sync? The last thing you need
> > is two really different versions of the hardware description.
> 
> concerning the instruction set and a certain set of constants,
> there is a way to keep things synchronized. but it's only superficial :
> architectural changes won't be kept synch'ed with m4.
> 
> i prefer to work at VHDL level : with an assembler, we can
> generate binaries that will be executed by the VHDL simulator itself.
> This is a powerful way to verify that our RTL code is valid.
> 
> when the RTL code is ok, we can re-write and simplify it in C,
> which will be certainly much faster ...
> 

Humm, it will better to do the opposite. So you can compare a golden
model to your much more long and complexe VHDL code.

SystemC was build for such task (cf. www.systemc.org). Does anybody have
a try ? Maybe i will try to write my vison of the pipeline with it. It
could much simpler to write it that way and then porting it in VHDL.

nicO

> > Ben Franchuk --- Pre-historic Cpu's --
> > www.jetnet.ab.ca/users/bfranchuk/index.html
> WHYGEE
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