Hi once more, gaetan@xeberon.net wrote: [...]
If you think it's too tight, put the inverters in front of the MUXes. You will need twice as many of them, but that's an affordable price. If that doesn't help, duplicate and move the input row of the adder (a row of half adders), too. That should give you enough time to decode the size field.or similar. That will add some latency before the subtractor. After that, you should have enough room for a row of 4-bit adders (d=4/t=6) and input inverters for one operand (d=1/t=1), maybe even for the final CLA (d=5/t=6 from the beginning of the adder).mode decoder d=1, 2 inverter d=1 4bit adder d=4 it's already d=6 (or 7)...
Yes. But I suggest you use 4-bit adders as building blocks. With one level of CLA/CSV, you'll get 16-bit adders, and another level extends the adder to 64 bits (or 2x32 if the final CLA has a SIMD split). If you go to 8 bits first, the total latency will be higher.will I have to make a carry select tree for mantissa adder like in the CSAdd if i split the mantissa in 8x8bit adders?
Don't worry. Remember the Golden Rules of Design:ok thank you very much. !! If i count well, i'm far from 4 stages for fadder... it will take at least takes 6 cycles... :'(