Re: [f-cpu] use of 1r1w regfile for our 3r2w regfile

[nicolas.boulay@ifrance.com]

Le Samedi 14 Juin 2003 10:37, Michael Riepe a écrit :
> On Sat, Jun 14, 2003 at 08:56:42AM +0000, Nicolas Boulay wrote:
> [...]
>
> > > This is what I consider the "worst case".
> >
> > But is that good or not ? 4x 1r1w regifile will be ~30% faster than a
> > true 3r2w.
>
> The worst case is, by definition, always bad (or even worse ;).

There is a miss understanding. The worst case the case where it slower. 3r2w 
SRAM memory are ~30% slower than 1r1w SRAM. But if we use 1r1w SRAM bank 
there is some collision that "could" be avoid by the compiler (otherwise you 
loose one cycle).

I can't say was is worst. It fully depend on compiler.

So big latches array will be oustandly slow.

nicO
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