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Re: [f-cpu] about Gaetan's work


Yann Guidon a écrit :


usually, it's the .vhdl file that has the name of the unit,
it's not a big one. for example :
http://f-cpu.seul.org/whygee/f-cpu/f-cpu/vhdl/eu_asu/asu.vhdl


entity EU_ASU is
   port(
       -- operands
       Din_0    : in F_VECTOR;
[...]
       Dout_3   : out F_VECTOR
   );
end EU_ASU;

architecture Struct_1 of EU_ASU is
   use work.IAdd;    -- make instantiated entity visible

   component IAdd
       generic (
           WIDTH : natural := 64;
           PIPELINED : integer := 0
       );
       port (
           A : in std_ulogic_vector(WIDTH-1 downto 0);
[...]
           Yh : out std_ulogic_vector(WIDTH-1 downto 0)
       );
   end component;

   signal dummy : std_ulogic := '0';
begin
--pragma synthesis_off
   assert UMAX mod 64 = 0
       report "UMAX must be an integer multiple of 64"
       severity failure;
--pragma synthesis_on

   adder : IAdd
       generic map (WIDTH => UMAX, PIPELINED => 1)
       port map (
           A => Din_0,
           B => Din_1,
           Sub => Subtract,
           Sat => Flags(12),    -- as defined in the manual
           Sig => dummy,
           Inc => dummy,
           Avg => dummy,
           U => Size(2 downto 0),
           Clk => Clk,
           Rst => Rst,
           En => En,
           Y8l => Dout_0,
           Y8h => Dout_1,
           Yl => Dout_2,
           Yh => Dout_3
       );
end Struct_1;

i don't see where a clone wrapper is?
i mean, it only instanciate a IAdd.
a clone wrapper should instanciate WIDTH/64 ones, no?


For the rest, i still haven't read enough of your code and report.
if you need to correct a lot of your spelling, grammar
and conjugation problems, i can help however :-)
first hint : "décalage" has only one "l" :-)


yes, yes, yes...
i added a french dictionnary to my TeX-editor (TeXnicCenter)...


though i guess it won't correct grammar and conjugation problems :-)

/me slaps YG with a large trout


good evening,
YG

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--

~~ Gaetan ~~
http://www.xeberon.net


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