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Re: [f-cpu] registers
On Sun, Oct 06, 2002 at 02:48:54AM +0000, Mohamed Ali Kilani wrote:
> Here is the WE summary: division, division and even more division ;)
>
> SRT with radix 2 is definitely the way to go in our case.
I came to the same conclusion :)
> I guess you are planning to fit an iteration in one cycle so we maintain
> 1bit/iteration throughput. The only way that I see to acheive this, for
> larger chuncks than 8 bits, is using CSAs for partial reminder(PR)
> computation and archiving it in redundant form.
>
> On the other hand, this architecture probably would work pretty good for
> the SIMD datapath.
That's right.
> I think you said that you a block diagram of the Divider you're
> designing. I would be glad to see it.
That was somebody else. But the picture is pretty simple: The operands
are normalized and fed into the SRT core. <n> cycles later, the core
delivers <n>-bit quotients and remainders, both in redundant form.
If the remainders have the wrong sign, the result is corrected. Finally,
the result is denormalized and converted back to normal binary encoding.
> If you could also incorporate the code you have in the repository on
> seul.org so I can be really up to date.
It's not finished yet, and I never release code that doesn't work.
> By the way, I have a general question about SIMD registers. I have read
> in the manual that any 64 bit general purpose register would have a flag
> indicating if it is a SIMD register or not. how about the SIMD mode?
No, that's wrong. Instructions have a SIMD flag, but not registers.
--
Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
"All I wanna do is have a little fun before I die"
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