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Re: gEDA-user: Plane is shorting a net?



I have occasionally run into symptoms like this with no obvious cause.   I am now on the 
lookout for the first sign of this, so I  can get it to be a repeatable bug so we can debug it.
What I do to help get practical results in the face of bugs is to make a very easy to use backup
method, and sometimes to use the built in backups that are done as the program crashes.

My on-purpose backups are done by running a script that does some copying of 
.sch, .net .pcb files and also my symbol libraries and footprint libraries.   This burns some
disk space, but it compresses very far and the disk is for using huh?  As often as I do this
with name suffixes like alphabet letters, then I can go back to know good states of my design.

Sometimes I can grab parts of a design from previous and copy them in by using the buffer and 
loading renamed versions of pcb drawings without shutting down pcb (keeping the buffer contents).

My scripts are short and quick to type:
./mkbk zd   

is an example of a command to make a backup with name suffix .zd which means
to me, "The 30th save of this design", since it is one pass through a-z, then a thru d also.
I burn plenty of disk space while making a pcb drawing -- It's a week of your life often,
why not back it up?

The next habit to get into is to run the optimize ratnest lines and
drc check very frequently also so you find a problem before you have added much,
since highlighting shows you the "now" state, and cannot tell you about history.
If you have that habit in place, you can often use undo to get back to a good state,
and even better, you can use your short term memory to try deleting things that are 
shorted.  Also turning off planes is good for getting a clue as to the short...you'll recognize
merged nets then that are covered when gnd and volt planes are visible


=======================

> Have anybody idea on how i can debug and solve my problem?
> 
> This is hard. The highlighting algoritm makes on me an impression it's
> in such cases useless. It always highlights the whole plane and you don't
> see anything. You have to try deleting various pieces of circuit until
> you strike the one with the short.

Finally, i delete all the elements involved, tracks, components, plane,
etc... re-synchronize with sch, re-place, re-route, re-plane, etc...
And the problem goes away! Don't know exactly why... :(

Thanks,
Christian
-- 
John Griessen    Cibolo Design       Austin Texas, linux counter #249315