gEDA-user: Assertion based verification using VCD and VHDL

[Darryl Dieckman <ddieckma@cliftonlabs.com>]

Hi,

I am trying to locate an open-source tool chain that I can
use for assertion based verification of a design.  I have
read about PSL/Sugar and the Open Verification Library (OVL).
It looks like OVL would allow me to add verification to
a VHDL design which would work great while my design is
in VHDL.

However, my digital design is eventually fabricated as a full custom
VLSI layout.  I extract SPICE for the design and run simulations
of the design in SPICE.  I then take the raw output from
the SPICE run and generate a VCD (value change dump) file.
Currently I use something like GTKWave to visually inspect the
digital response of the circuit.

What I would really like to do is to be able to use my VHDL
test bench to verify my SPICE simulation to make sure that
there were no errors introduced during the layout phase.  I
could do this by running my VHDL test bench against the SPICE
results.  It seems that the one piece that I am missing is
a 'vcd2vhdl' type program that could take a VCD file and generate
a VHDL entity/architecture that I could simulate.  In theory
the same signals would exist in both my VCD and VHDL designs and
therefore my assertions could be applied to the converted VCD
entity/architecture.

So, does anyone know of a 'vcd2vhdl' type tool?  It seems like
a basic tool would be pretty simple to develop, but why invent
the wheel if I don't have to.

Finally, is there a better way to verify the operation of a
digital circuit simulation done using SPICE?

Darryl Dieckman
Senior Engineer
Clifton Labs, Inc.
www.cliftonlabs.com