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Re: gEDA-user: Polygon clearance for pairs in PCB




On Apr 8, 2006, at 11:58 AM, Levente wrote:

On Sat, 8 Apr 2006 10:35:28 -0400
DJ Delorie <dj@xxxxxxxxxxx> wrote:

You want the "solid thermals" option we've been talking about.

It would be nice to be the default for vias, since you don't solder anything into a via, do you?

Blue wires ;-)

John Doty              Noqsi Aerospace, Ltd.
jpd@xxxxxxxxxxxxx