Re: gEDA-user: Re: Efficient Memories

[lingwitt@xxxxxxxxxxxxx]

On 7 Apr 2007, at 10:57:19 AM, Stephen Williams wrote:

*sigh* This is bad enough to be called a bug. If you have a small

example that triggers this "aspect", can you file it as a bug report?

You have my permisison to nudge its priority up to "6" because this

is actually quite embarrassing:-(

I've made a bug report. In the report, I take the opportunity to ask the following

question:

Why aren't operations on variables--including arrays, regs, and nets of any

size--extremely fast in Verilog when compared to those of other language

implementations?

Other language implementations--like Python, for instance--do not know the

types of values to which variables will be bound, so it is hard to

optimize.

However, Verilog deals only with one kind of datum: numbers (of a certain size).

It seems like Verilog simulations should be much faster than any

commensurate Python simulation, but this is just not the case--at least for

iverilog.

Thanks.

_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user