Re: gEDA-user: terminators

[Steve Morss <smorss@xxxxxxxxxxxxxxxxxxxxx>]

I built a very similar circuit using an Altera FPGA and a 100MHz SDRAM 
with good results.  To keep things easy, I did a couple of things.  One, 
I kept the signals to the SDRAM as short as possible (around an inch 
long, in most cases).  Second, I made sure that the clock that the SDRAM 
controller sees and the clock of the SDRAM have minimal skew.  I did 
this by running the original clock into the FPGA and then running it out 
2 pins.  One went to the SDRAMs and the other went back into the FPGA, 
but the etch length was the same as the length that went to the SDRAMs.  
Then, I used a PLL in the FPGA to "look" at the arriving clock and skew 
it (which are really the output clocks) to match the clock of the SDRAM 
controller.  That way, I could be sure that the clock that the SDRAM 
sees and the clock of the controller were the same.  Without that, it's 
very hard to meet all the max/min setup and hold times of the SDRAM and 
SDRAM contoller.

Steve


DJ Delorie wrote:
>> That's what I'd do.  At the sort of volumes you and I work with it's
>> a lot cheaper to use a FPGA big enough to include
>> chipscope/signaltap even in the full design than to allow for an LA
>> hookup.
>>     
>
> I'm limited to QFP packages, though.  I picked the 3A family for some
> reason, ah, power - the 3A doesn't need a 2.5v interface block.
> I haven't tried synthesizing into the 3A yet to see how much space I'm
> using.
>
>   
>> Why not just use chipscope?  I thought you could get that for free
>> these days (although admittedly I use Altera mainly for free Signaltap
>> myself).
>>     
>
> Well, if chipscope is freely downloadable, I'm OK with that.
>
>   
>> Hard to believe the LA expects signals that fast without active probes.
>>     
>
> Well, I said Ms/s, not MHz.  It's mostly useful for measuring skew and
> jitter relative to other pins.  I usually run at one of the slower
> speeds, as the LA's compression doesn't work at the fastest speed.
>
>
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>   



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