[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]
Re: gEDA-user: input/output ports gschem
Many thanks for the info!
The example about hierarchy design using ports, was pretty useful John.
On the other hand, I see that instead of applying a netname to every
signal connected to an i/o port, I just have to add the pinnumber/label
to the net= attribute of the port(The link was very useful Duncan,
didn't see it surfing on the wiki brefore).
So, now I know how to do it. BUT I feel like gschem could consider
net=SIGNALX to be an implicit form of net=SIGNALX:1 since specifying a
pin in a one pin symbol doesn't make much sense to me. I think this is a
very simple feature to implement. Would be great if it does so.
Best Regards, Felipe.
--
Felipe De la Puente Christen
Mobile Phone : +56 9 93199807
MSN/GTalk : fdelapuente@xxxxxxxxx
On Thu, 2010-04-15 at 14:25 -0600, John Doty wrote:
> On Apr 15, 2010, at 1:06 PM, Felipe De la Puente Christen wrote:
>
> > Hi,
> > I did a design using input, output, and io ports based on the
> > input-2.sym available in the library. I thought that the net attribute
> > would make the net between the component's pin and the port to be named
> > the same as the port's net attribute, but I was wrong and it's still
> > necessary to put a netname on the nets involved to make the logical
> > connection at the other side(another port + net + component's set).
> >
> > So the question(suggested by DJ) is: How are these input/output
> > graphical ports supposed to work? Are they merely graphic things, or
> > does that net attribute have a special/useful function?
>
> They are for hierarchy, not for making connections between sheets at the same level.
>
> For connecting sheets at the same level, the netname attribute is the thing to use. For clarity, I like to group such connections into busses (which in gschem are just graphical).
>
> For hierarchy, match pinlabel on the symbol representing the subcircuit with the refdes an the connection symbol within the subcircuit schematic.
>
> Here's a fragment of such a design. In particular, look at the DACtoClock block on sheet 2 to see how hierarchy works, and the connections between sheets 1 and 2 for usage of netname and busses.
>
>
> John Doty Noqsi Aerospace, Ltd.
> http://www.noqsi.com/
> jpd@xxxxxxxxx
>
>
_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user