[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

Re: gEDA-user: input/output ports gschem



As Stefan Salewski reported, I missed in my attachments:

RES-1016-630-240.fp -> RES-1016P-630L-240D__Yageo-MFR-25.fp

is a symbolic link I made to a Luciani footprint.

Sorry for the inconvenience.

Armin

Armin Faltl wrote:
Hi,

I'm new in this group but here because I seek help to fight bugs.

To implement a feature, that has to be understood by several
converters and ev. pcb is by no means simple. In particular
the effort to save someone typing ":1" by creating a special case
is much better spent for getting the basics in pcb right.

So, now I know how to do it. BUT I feel like gschem could consider
net=SIGNALX to be an implicit form of net=SIGNALX:1 since specifying a
pin in a one pin symbol doesn't make much sense to me. I think this is a
very simple feature to implement. Would be great if it does so
I ask/challenge everyone on the list to point out to me, what's wrong with my schematic attached - I think nothing. Hopefully it triggers a bug with your installations as well. The culprites it was indicated to me might be bad symbols from gschem - that would be capacitor-1.sym and resistor-2.sym then - hardly used by anyone I suppose.
The problem appears in the ratsnet optimizer - it's the
  "Can't find XXX pin N called for in netlist."-bug

Here my analysis so far, in the hope that it is useful:

the symbol I use is "capacitor-1.sym" from the standard library.
I checked it's contents and it has 2 pins named "1" and "2".
There is also another "capacitor-1.sym" in
/usr/share/gEDA/sym/gnetman/capacitor-1.sym, however,
the symbol information is passed to pcb only via the netlist,
the generated board-file and the command-file - no explicit
mention of a symbol is made in them, as opposed to the schematic,
where the symbol files are referenced.

After trying 3 different footprints: yours, a self-drawn and one
from the m4-collection, all with the same result I'm desparate.
I checked the pins 1 by 1 in the files, clearly not my primary intention.

There are two another good reasons to believe, that pcb is
fundamentaly broken:
a) the same resistor symbol and footprint combo has 2 instances
 that work in the board and 1 instance, that doesn't
b) when invoking the rat-optimizer, the log-messages complain about
 missing pins, thats names do not match to the net-pinnames, while
 the netlister shows the pins correctly
 - when I route a copper trace that is not found by the rats
 (disabling the auto-drc), and call the rats optizer again,
 I get a warning, that pin hugo-1 is shorted to some_net
 while in the netlister some_net cleary lists hugo-1.
 In the rats there is a "Can't find hu pin 1 called for..." instead.

This is an indication of redundant datastructures and buggy mapping.

*end analysis*

It would be intelligent btw, to mention the netname on which the missing
pin appears in the log output, to aid debugging - either of pcb or the schematic.

Best Regards, Armin Faltl
------------------------------------------------------------------------



_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user


_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user