Re: gEDA-user: wishful UI

[John Doty <jpd@xxxxxxxxx>]

On Aug 9, 2010, at 8:44 AM, Stefan Salewski wrote:

> On Sat, 2010-08-07 at 11:33 -0600, John Doty wrote:
>> On Aug 6, 2010, at 6:42 PM, Andrew Poelstra wrote:
>> 
>>> On Sat, Aug 07, 2010 at 12:51:34AM +0200, Stefan Salewski wrote:
>>>> 
>>>> The current status of my mind:
>>>> 
>>>> Having net classes in gschem would make all much easier.
>> 
>> Nothing new needs to be added to gschem: you can attach arbitrary
>> attributes to net segments already.
>> 
>> The place where you need a new capability is gnetlist: a gnetlist back
>> end cannot currently query a net segment for its attributes.
>> 
> 
> Indeed, for my proposal of net classes defined in gschem clean modular
> design should still work. For this case flow of information is from
> gschem to PCB. But we should teach gschem that a large net can consist
> of multiple connected subnets, for example a 3.3V net, with width traces
> from DC/DC-Converter to FPGA, and narrow traces to some other devices.

There is no need to teach gschem anything to do this. It's like the geometric parameters for VLSI devices. All that's needed is that the relevant gnetlist back ends understand how to pass attributes like w=, l=, m=, etc. downstream.

> 
> Then we have to teach gnetlist to process this,

Not gnetlist itself, just the relevant back ends.

> and to teach PCB program
> to understand it.

Does any PCB layout program support this? Its semantics would be a good place to start. Remember, "pcb" isn't the only layout path we support.

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx




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