Re: gEDA-user: Bug fixed?

[Stephen Williams <steve@xxxxxxxxxx>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

David Howland wrote:
|> In this case, you'd get better results if you specified a more
|> specific arch=, rather then let it make the generic LPM devices.
|> The problem here is that there are just some code generator functions
|> missing for the architecture you are targetting.
|
|
| It seems to me that the arch= only targets Xilinx virtex parts.  If O'm
| not using those devices, then i have to use arch=lpm, yes?

Yes, true.

In principle, "A" arch= families can be added by adding the C code
in the tgt-fpga directory, although I suspect Altera backend stuff
takes in EDIF/LPM directly.

And of course, one option is to fill out the LPM cases in the
tgt-fpga code generator. This suggests that the answer to your
original question is "Yes, some coding is still required for
synthesis using Icarus Verilog." In the case you are describing,
though, the code is limited to the code generator, the core
synthesizer seems to have done enough already.

- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.0.7 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

iD8DBQFBv4YZrPt1Sc2b3ikRAvQsAJ4tsjabjTqgqFexD5J75kykS8FdmgCgx3Dj
r/EwPdIVEHPDoOPLuZRm4bQ=
=BO2C
-----END PGP SIGNATURE-----