Re: gEDA-user: Heavy Symbols and such

[Steve Meier <smeier@xxxxxxxxxxxxxxxxxxx>]

What is the deffinition of a heavy symbol? And secondly why put a data
base behind one? I have been pondering this from several levels.

One level is about how heavy large components have become and the tasks
that are used in building a working programed printed circuit board.

Take a large fpga that has a large number of io pins that can have many
different functions. these are typically broken up into groups other
wise called banks.

On a bank by bank basis it is possible to sellect the following logic
families

3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
3.3-V PCI-X mode 1
LVDS
LVPECL
Differential 1.5-V HSTL Class I and II
Differential 1.8-V HSTL Class I and II
Differential SSTL-18 Class I and II
Differential SSTL-2 Class I and II

Within a bank a pair of io pins can be used differentialy or as single
ended inputs. At lay out time pin swapping to detangle the netlist
becomes very attractive. Which pins can be swapped?

On a second level, even a resistor has limitations. For a given
manufacturor of a given product line there exists only a finite number
of resistance values? To support manufacturing I would like to know what
are the options for a particular package? Can I expect the package to
survive the expected power levels?

On a third level, I would like to tie models and/or code (verilog, vhdl,
spice) to a symbol and have the ability to generate simulatable netlists.

So packages, must have correct pin numbers and available land patterns,
part numbers must be correct to generate boms and thus purchase orders.
To support layout the netlist needs to tell the layout program what can
be swapped with what and the layout program needs to tell the schematic
program what was swapped so that the schematic can be corrected for
reality. Idealy the layout needs to be back-integrated into the
simulation models for looking for tdr effects, paracitic capacitance etc.

The schematic output needs to be capable of generating pin to signal
descriptions for importing into proprietary software to support fpga or
asic development.

Why do we need to have heavier symbols... well in my opinion because the
world of elcetronics is getting more complicated not less and light
symbols presume a simple world and heavy symbols support the real world.
But best of all is a comprimise where a data base generates or at least
supports the symbols and simulations needed.

Steve Meier

P.S. If you were looking for a deffinition, well so am I. Please write
your ideas... If there is one truely beautifull idea behind open
knowledge it is the idea of sharing ideas.



Randall Nortman wrote:
> On Tue, Dec 04, 2007 at 06:36:45PM -0800, Steve Meier wrote:
>   
>> I am becomming more and more a proponent of heavy symbols or even a data
>> base then can generate heavy symbols. One of the really nice things
>> about geda is its tollerent or flexible and that heavy symbols could
>> easily be implemented. So the question is... is there enough support in
>> the geda community to create a heavy symbol library?
>>     
>
>
> I've been noticing this whole heavy vs. light debate for a while, but
> not really following it.  A heavy symbol is something that is fully
> specified, including footprint, right?  Does that go all the way to
> particular manufacturer part numbers?  A light symbol would be what
> the majority of the included library is right now -- generic symbols
> with no footprint specified, using generic pin assignments (which
> sometimes do not agree with reality for certain parts), right?
>
> Personally, when I need a "heavy" symbol, djboxsym does the job in a
> jiffy.  (Thanks, DJ!)  I use resistor, capacitor, diode, etc. symbols
> from the included library, and pretty much everything else comes from
> djboxsym.
>
>   



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