Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[John Doty <jpd@xxxxxxxxxxxxx>]

On Dec 6, 2007, at 2:46 PM, Steve Meier wrote:

> As long as its semantics is well enough deffined that I can write a
> macro to read and write its file formats then why not?

It might be nice, but who knows what it is, and how to reasonably map  
it onto our problem? Al's always selling Verilog. But I went and  
bought the book he recommended on Verilog-AMS, and it was mostly more  
sales pitch.

I AM REALLY TIRED OF THE VERILOG SALES PITCH.

Is there any *substance* here beyond the digital HDL?

Al, *show* us something *real*. I don't necessarily mean you need to  
write something: a pointer to something would be just fine (as long  
as it's not just more pitch). But the more you push what seems to be  
vapor, the more I'm going to ignore it. And I suspect I'm not the  
only one...

>
> al davis wrote:
>> On Wednesday 05 December 2007, Michael Sokolov wrote:
>>
>>> al davis <ad151@xxxxxxxxxxxxxxxx> wrote:
>>>
>>>> Why invent a new language?  Either Verilog-AMS or VHDL-AMS,
>>>> the = structural subset, has everything you need.
>>>>
>>> I needed something I could implement by myself without any
>>> help from the outside world and without any dependencies.  It
>>> also needs to run under UNIX Version 7 and cannot depend on
>>> anything other than a K&R C compiler plus standard UNIX stuff
>>> that came with V7 (such as M4 that everyone hates so much but
>>> which I absolutely adore).
>>>
>>
>> That is why I said "the structural subset".  It meets all of
>> those requirements.  In this case, Verilog is lighter than
>> VHDL.
>>
>>
>>
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John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx




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