Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[Dan McMahill <dan@xxxxxxxxxxxx>]

John Doty wrote:
> On Dec 7, 2007, at 3:45 AM, Dan McMahill wrote:
> 
>> John Doty wrote:
>>> On Dec 6, 2007, at 2:46 PM, Steve Meier wrote:
>>>
>>>> As long as its semantics is well enough deffined that I can write a
>>>> macro to read and write its file formats then why not?
>>> It might be nice, but who knows what it is, and how to reasonably map
>>> it onto our problem? Al's always selling Verilog. But I went and
>>> bought the book he recommended on Verilog-AMS, and it was mostly more
>>> sales pitch.
>>>
>>> I AM REALLY TIRED OF THE VERILOG SALES PITCH.
>>>
>>> Is there any *substance* here beyond the digital HDL?
>>>
>>> Al, *show* us something *real*. I don't necessarily mean you need to
>>> write something: a pointer to something would be just fine (as long
>>> as it's not just more pitch). But the more you push what seems to be
>>> vapor, the more I'm going to ignore it. And I suspect I'm not the
>>> only one...
>> I use verilog-A quite a bit and it is a huge benefit to me in real  
>> world
>> (not just CAD vendor white paper) applications.  Here is a simple
>> example.  You can generate a much more complex stimulus to drive a
>> circuit under test with.  Yes you could use <insert external program
>> name here> to generate piecewise linear source, but it really can be
>> much more convenient to have it integrated with the simulator.  Also,
>> suppose the source needs to react to some signal in the test  
>> schematic.
>>   PWL sources don't do that.  Verilog-A does.  Before I had access to
>> AMS, I had several cases where Verilog-AMS had exactly the missing
>> feature I needed to greatly simplify and expand some simulation  
>> coverage.
>>
>> I think a big part of the issue here is this:
>>
>> - there are no verilog-AMS implementations which are freely  
>> available or
>> even priced in the few thousand dollar range.
>>
>> - there are no verilog-A implementations which are freely available.
>> I'm not sure if you can get one for a few thousand or not.
> 
> But even worse for the purpose of understanding its possible use in  
> gEDA, it seems impossible to find real information and practical  
> examples. There's a lot of hype. but where is the *substance*?

Right, the lack of practical examples is largely tied to most of them 
having been developed in the context of a proprietary development.  Same 
reason why its hard to download an example spectre netlist of any 
substance.

>> The end result is unless you're spending 10's of thousands on CAD
>> software, you don't have access to these tools and as such people are
>> not using them for hobby projects.
> 
> It's not just hobby projects. I'm a professional physicist, and the  
> things I design are state of the art scientific instruments, but I'm  
> not a full time circuit designer and I don't have the EDA tool budget  
> that a full time designer would have. gEDA has been extremely  
> valuable to me.

My comment about hobby projects is simply that those are the ones where 
people are largely free to post details in a public forum.

I did think of one example.  There were a handful of papers from a TI 
guy in JSSC and/or TCAS a couple of years back.  He did some very in 
depth modeling of a pretty complex RF transmitter chip using VHDL.  One 
of the key things which enabled VHDL was missing from verilog-HDL (reals 
as port variables) but verilog-AMS has that.

>>   Since the projects using those tools
>> are all proprietary, there is little opportunity for users here to  
>> give
>> much more information beyond "these tools are worthwhile".  No  
>> concrete
>> examples.  Besides, its not like most people here could run a concrete
>> example anyway because of the lack of an implementation that is  
>> even in
>> the "pretty darn expensive but I want one at home anyway" price range.
>>
>> I could spend time an put together a non-proprietary example, but it
>> would be a fair amount of effort because to fully appreciate the
>> capability you need a problem of some complexity.  And then at the end
>> of the day I'd have an example that can't be run until gnucap has
>> verilog-A or verilog-AMS.  I for one am thrilled at how much Al is
>> working towards having that capability.
> 
> If it's anything like as good as Al claims it will be, I will be  
> happy to use it. But I have little confidence, given the present low  
> signal to noise ratio.

It is not just Al.  A more accurate statement might be that around here 
not many have access to verilog-A or verilog-AMS implementations and 
hence there are not many first hand experiences to share.  I've not 
heard anyone here say "I tried out verilog-A or verilog-AMS for my 
projects and it just didn't work out".  The few cases I've encountered 
of that in other places ended up being traceable to a pilot error.  The 
pilot errors could be analogous to doing things like the following in 
matlab:

% multiply the elements of my two 100,000 length vectors
for i=1:length(x)
z(i) = x(i)*y(i);
end

yeah it works, but if you use z=x.*y like the tool intends it works way 
better.


Don't forget that the more advanced models for modern devices are 
largely developed in verilog-A.  Look at EKV for example.  That is 
pretty much *the* path towards getting a newly developed model 
formulation (as opposed to model parameters) into a wide array of 
simulators.  If thats not a proof of the utility of at least one 
application of verilog-A, I don't know what is.  The old "write it in c" 
approach required substantial porting effort.

-Dan




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