Re: gEDA-user: overlapping via changes

[DJ Delorie <dj@xxxxxxxxxxx>]

Kai-Martin Knaak <knaak@xxxxxxxxxxxxxxxxxxx> writes:
> Does pcb complain if the user tries to overlap vias. Or does it just 
> silently refuse to put the via?

It does, and always has, printed a message to the message log.

> Back then when I used protel we actually had cases where overlapping
> were holes deliberate. The hole had to be non-round and clad with metal. 

Right.  That's why we need to preserve these "cheats" once the user gets
them into the pcb file.


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