[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: gEDA-user: Gschem footprint attributes in PCB

To: Geda-user <geda-user@seul.org>
Subject: Re: gEDA-user: Gschem footprint attributes in PCB
From: Egil Kvaleberg <egil@kvaleberg.no>
Date: 10 Feb 2003 09:00:40 +0100
Delivered-to: archiver@seul.org
Delivered-to: geda-user-outgoing@seul.org
Delivered-to: geda-user@seul.org
Delivery-date: Mon, 10 Feb 2003 03:00:45 -0500
In-reply-to: <3E470D49.9080200@sympatico.ca>
Organization:
References: <3E470D49.9080200@sympatico.ca>
Reply-to: geda-user@seul.org
Sender: owner-geda-user@seul.org

On Mon, 2003-02-10 at 03:24, Mark Cianfaglione wrote:
> I've been working with gschem and pcb for a couple of days now to 
> familiarize myself with the tools and I've noticed that the footprint= 
> attribute in gschem does not match up with the footprint coding in 
> pcb.

A while back I did make a proposed suggestion for footprint names in
geda, mostly based on the footprint names that already seemed to exist
in the geda "world". I also made a "pcb" extension library "geda" to
support these.

There were some controversy wrt. the exact naming. It turned out that
there really is no "official" standard which can be used universally, so
I ended up by using names that seemed to be broadly accepted and easy to
memorize. 

I will summarize the naming conventions thus far. This is not a
"scientifily correct" description, I'm just assuming knowledge of
various industry package names and conventions. 

The major cons are: It is not perfect, far from complete, not in
accordance to one particular standard.

The major pro is: It exists, i.e. better than nothing.

>From my perspective, the "pro" far outweighs the "con" here. If someone
has a better suggestion, I'm all for it. But since it has been a couple
of months since this was first aired, it should probably be on the table
quite soon?

My suggestion is this should be include in the Geda documentation as
"preferred" naming

Egil

--------------------------------------------------------------------------

Notes:

	Unless otherwise noted, numerical pin names will be used,
 	starting from 1.

	<n> is for the pin count.

	<m> is for the pin spacing in mils.

	SMT means surface mount, other components are through-hole.

Dual in line packages with up to 22 100 mil spaced pins and 300 mil row
spacing are called DIP<n>. 

Dual in line packages with 24 or more 100 mil spaced pins and 300 mil
row spacing are called DIP<n>N.

Dual in line packages with 100 mil spaced pins and 400 mil row spacing
are called DIP<n>H. 

Dual in line packages with 24 or more 100 mil spaced pins and 600 mil
row spacing are called DIP<n>.

Shrink dual in line packages with up to 24 70 mil spaced pins and 300
mil row spacing are called SDIP<n>.

Shrink dual in line packages with more than 24 70 mil spaced pins and
400 mil row spacing are called SDIP<n>.

Single in line packages with 100 mil spaced pins are called SIP<n>N. See
also JUMPER, below.

Small outline SMT packages with up to 16 50 mil spaced pins and 150 mil
total width are called SO<n>.

Small outline SMT packages with more than 16 50 mil spaced pins and 150
mil total width are called SO<n>N.

Small outline SMT packages with 50 mil spaced pins and 200 mil total
width are called SO<n>M.

Small outline SMT packages with up to 20 50 mil spaced pins and 300 mil
total width are called SO<n>W.

Small outline SMT packages with more than 20 50 mil spaced pins and 300
mil total width are called SO<n>.

Small outline SMT packages with 44 or more 50 mil spaced pins and 525
mil total width are called SO<n>.

Metric shrink small outline SMT packages with 0.65 mm spaced pins and
323 mil total width are called MSSOP<n>. (?)

Metric shrink small outline SMT packages with up to 44 0.65 mm spaced
pins and 420 mil total width are called MSSOP<n>W.

Metric shrink small outline SMT packages with over 44 0.65 mm spaced
pins and 545 mil total width are called MSSOP<n>W.

Shrink small outline SMT packages with 0.25 mil spaced pins and 420 mil
total width are called SSOP<n>W.

Quarter size small outline SMT packages with 0.25 mil spaced pins and
244 mil total width are called SSOP<n>.

Thin small outline SMT packages with 0.2165 mil spaced pins and 535 mil
total width are called TSOP<n>.

Thin small outline SMT packages with 0.20 mil spaced pins and 795 mil
total width are called TSOP<n>A.

Thin small outline SMT packages with 0.20 mil spaced pins and 559 mil
total width are called TSOP<n>B.

Thin shrink small outline SMT packages with up to 28 0.26 mil spaced
pins and 260 mil total width are called TSSOP<n>.

Thin shrink small outline SMT packages with over 28 0.20 mil spaced pins
and 319 mil total width are called TSSOP<n>.

Plastic leadless chip carrier SMT are called PLCC<n>.

Plastic leadless chip carrier with pin socket are called PLCC<n>X.

Quad-side flat pack SMT are called QFP<n>.

Zig-zag in-line package are called ZIP<n>.

Axial non-polar components (typically resistor, capacitor) are called
ACY<m>.  

Axial diodes are called ALF<m>. Pin 1 is the cathode.

Bottom lead (radial) non-polar circular component (typically capacitor)
is RCY<m>.

Bottom lead non-polar rectangular component (typically capacitor) is
BRE<m>.

Crystal is HC49, or other HC designations as required.

Dual in line style crystal oscillator is OSC8 or OSC14.

Conventional through hole LED is LED3 and LED5 for 3 and 5 mm
respectively. Pin 1 is plus. (NOTE: Should probably be changed to be in
line with diode convention!)

TO transistors are TO5, TO92, TO126, TO220 etc. Suffixes may apply, e.g.
TO126W is for wide, TO126 is for standing, TO126SW is for standing,
wide. 

Single row 100 mil pin spacing jumpers are JUMPER<n>. The main
difference compared to single in line pachage is the hole size.

Dual row 100 mil spacing headers with DIP pin numbering are HEADER<n>_1.
Note that <n> is an even number. 

Dual row 100 mil spacing headers with ribbon cable numbering are
HEADER<n>_2. Note that <n> is an even number. 

Angled full header connectors with latches are DIN41651_<n>.

Standing full header connectors with latches are DIN41651_<n>S.

DSUB connectors female are DB<n>F.

DSUB connectors male are DB<n>M.

Female DIN card-to-card connectors are DIN41612C<n>F. Add S suffix for
standing.

Male DIN card-to-card connectors are DIN41612C<n>M. Add S suffix for
standing.

RJ AMP modular connector with screen are RJ11, RJ12 and RJ45.

Standard SMT resistors, inductors, capacitors etc are 0201, 0402, 0603,
0805, 1206, 1210, 1806, 1812, 1825, 2020, 2706.

Tantalum SMT capacitors (pin 1 is plus) are EIA3216, EIA3528, EIA6032,
EIA7343.

SMT electrolytics are designated by can diameter in 1/10 mm: SME33,
SME43, SME53, SME66, SME84, SME104.

SOD diode SMT packages use their standard package name, e.g. SOD80,
SOD87, SOD106A, SOD110. There are also SOD123, SOD323 with narrow pads.

SOT transistor SMT packages use their standard package name, e.g. SOT23,
SOT323. There is also an SC90.

SOT transistor SMT packages with numbering as for diodes (pin 1 is
cathode, pin 2 anode) are SOT23D, SOT323D.

4 pin SOT SMT packages are SOT89, SOT143, SOT223.

5 pin SOT SMT packages are SOT25 and SOT325.

6 pin SOT SMT packages are SOT26 and SOT326. 

-------------------------------------------------------------------------------

-- 
Email: egil@kvaleberg.no  
Voice/videophone: +47 22523641 Voice: +47 92022780 Fax: +47 22525899
Mail:  Egil Kvaleberg, Husebybakken 14A, 0379 Oslo, Norway
Home:  http://www.kvaleberg.com/

References:
- gEDA-user: Gschem footprint attributes in PCB
  - From: Mark Cianfaglione <mark.cianfaglione@sympatico.ca>

Prev by Date: Re: gEDA-user: Gschem footprint attributes in PCB
Next by Date: Re: gEDA-user: Fw: pcb 1.99n automake version DJ Barrow and Egil Kvaleberg m4 added to library
Previous by thread: Re: gEDA-user: Gschem footprint attributes in PCB
Next by thread: gEDA-user: RE: pcb 1.99n automake version DJ Barrow and Egil Kvaleberg m4 added to library
Index(es):
- Date
- Thread