Re: gEDA-user: Verilog 2001

[Stephen Williams <steve@icarus.com>]

[integral types and language support]

office@anydroid.de said:
>  Your reasons laying in performance  wasn't clear to me.

My point was that there are cases in a Verilog simulation where
4-value logic (0,1,x,z) doesn't really need to be fully simulated
and the simulation engine can use native integral types to represent.

For example:

    integer idx;
    for (idx = 1 ;  idx < 100 ;  idx = idx + 1) begin
        [stuff that reads idx]
    end

Even though Verilog presumes that idx may have x or z valued bits,
if I can tell at compile time that x or z values can never get into
idx, I can instead use a native integer to model it. In addition,
once I add support for integral types, you will be able to declare
idx like so:  "int idx" and the compiler will *assure* that x or z
bits can't get into the value.

Not having to account for x or z values for certain vectors should
make execution of a model faster.


office@anydroid.de said:
> Unfortunately my ftp program  shows me a 'permission denied' and
> sourcefork is still empty.

The ftp tarball on sourceforge is obsolete. We rely on CVS access
through sourceforge to access the test suite. This turns out to be
the only practical way, as it is continuously and gradually updated.

It is unfortunate that I don't have a list of supported features,
but there *is* a list of unsupported features in the README.txt
file. A positive list of supported features would be continually
out of date:-(
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
steve at picturel.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."