Re: gEDA-user: vhdl and gschem

["Chitlesh GOORAH" <chitlesh@xxxxxxxxxxxxxxxxx>]

On 2/11/07, Magnus Danielson wrote:
> However, in general what you do want to do is to design in input and output
>
> You want to go into the VHDL symbol table and use ipad-1, opad-1 and iopad-1
> which will map over to VHDL in, out and inout declarations of Std_Logic type.
> Assign the value of these to the name you want in the entity port declaration.
>
> There still isn't vectorization which would be nice in the long run.

Hello,
thanks for the tip,

However, with gschem when I try to add a component from the sym/vhdl/
folder, gschem does not find such folder. But if I rename that
sym/vhdl folder to sym/spice, gschem sees the *.sym files. Is it a bug
? 20061020 inside.

> There is even those pre-rolled for your delight. Check out:
> http://www.freemodelfoundry.com/

Thanks again for the tip :)

thanks,
Chitlesh
--
http://clunixchit.blogspot.com


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