Re: gEDA-user: vhdl and gschem

[Magnus Danielson <cfmd@xxxxxxxxxxxx>]

From: "Chitlesh GOORAH" <chitlesh@xxxxxxxxxxxxxxxxx>
Subject: gEDA-user: vhdl and gschem
Date: Sun, 11 Feb 2007 20:03:47 +0100
Message-ID: <13dbfe4f0702111103g58a70dcerfa93b67dc60f7a5e@xxxxxxxxxxxxxx>

Hi!

> Hello thre,
> 
> I'm trying to make a VHDL file from a mere simple half adder schematic:
> http://tux.u-strasbg.fr/~chit/half_adder/adder.sch
> 
> with:
> gnetlist -g vhdl adder.sch -o output.vhdl
> http://tux.u-strasbg.fr/~chit/half_adder/output.vhdl
> 
> However, I don't know how to create an entity with gschem. Can any one
> point how to make a simple one for my adder.sch ?
> 
> In my actual output.vhdl, the entity is "not found".

See comment from Carlos Nieves Ónega.

However, in general what you do want to do is to design in input and output

You want to go into the VHDL symbol table and use ipad-1, opad-1 and iopad-1
which will map over to VHDL in, out and inout declarations of Std_Logic type.
Assign the value of these to the name you want in the entity port declaration.

There still isn't vectorization which would be nice in the long run.

> My second question about the vhdl and geda is how can I simulate that
> output.vhdl file with ghdl when the generated output.vhdl comes with:
> component 7408 or 7086 in my case. how can I make ghdl read those
> particular components as their respective entities and architecture
> ("or", "and")? Should I create those entities by myself or is it there
> something automated ?

There is even those pre-rolled for your delight. Check out:
http://www.freemodelfoundry.com/

Cheers,
Magnus - guilty to the original VHDL backend which fortunatly have been maintained by others


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