Re: gEDA-user: vhdl and gschem

[Magnus Danielson <cfmd@xxxxxxxxxxxx>]

From: "Ostheller, Joel A. " <JOEL.A.OSTHELLER@xxxxxxxx>
Subject: RE: gEDA-user: vhdl and gschem
Date: Fri, 16 Feb 2007 17:49:38 -0800
Message-ID: <792402774609E243A786ED2AE77FCFEC03064EE6@xxxxxxxxxxxxxxxxxxxxxxxxxxx>

> Yes. Pick yourself up a copy of Peter Ashenden's "The Designer's guide
> to VHDL". Additionally you may want to get a copy of the IEEE VHDL LRM. 

It's number is IEEE 1076.

Hardcopy:
http://shop.ieee.org/ieeestore/Product.aspx?product_no=SH95294

Download:
http://shop.ieee.org/ieeestore/Product.aspx?product_no=SS95294

The listprice is 255 USD.

Regardless, I have good use for mine from time to time now. Much more as I
tried to pick it up.

> There is no reason to use schematic capture packages to do Verilog or
> VHDL. Some have claimed that using it to import your VHDL/Verilog such
> that it auto-generates a system block diagram is an acceptable use... I
> usually will give them that, but not much more. 

The main reason to have a VHDL backend is to allow the netlist to be passed
over to a VHDL simulation on board level. When doing VHDL-AMS the VAMS backend
(adapted by Bosch from the original VHDL backend, many good improvements)
is usefull when you want to do analog simulations (which may include chipscale
projects).

Using gschem as the main tool for VHDL design isn't going to get you far.
Using gschem for normal schematic design and then exporting the netlist for
simulation usage in combination with the descriptions of the various logical
circuits (models of chips or written designs) is however possible by using a
backend such as the VHDL backend.

If one wants to do serious board level simulations, one should be aware that
the model of the board which the VHDL backend generates is without timing, so
we don't know the delays. We would have to annotate it through SDF and frankly,
I am not sure if it is fit for direct use (could check the details, but I know
more senior folks are here which should know this at heart).

So, if you want to do some VHDL hacking, don't expect gschem/gnetlist to be the
tools to grease up the experience. It was never designed for it and is il-fit.
If your only job is to interconnect some VHDL blocks, then you are in luck.
You would still require sufficient VHDL knowledge to figure out the errors,
and frankly that would be much quicker resolved using a tool like EMACS rather
than gschem/gnetlist.

If you want to have a fairly good start, then download Xilinx Webpack which ISE
environment has plenty of help info on how various VHDL contstructs should be
done etc.

Personally I use EMACS for my professional design and EMACS/WebPACK for my
hobby use. Should have a crack at ghdl again.

Cheers,
Magnus


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