Re: gEDA-user: vhdl and gschem

[Andy Peters <devel@xxxxxxxxx>]

On Feb 16, 2007, at 6:49 PM, Ostheller, Joel A. wrote:

> Yes. Pick yourself up a copy of Peter Ashenden's "The Designer's guide
> to VHDL". Additionally you may want to get a copy of the IEEE VHDL  
> LRM.
>
> There is no reason to use schematic capture packages to do Verilog or
> VHDL. Some have claimed that using it to import your VHDL/Verilog such
> that it auto-generates a system block diagram is an acceptable  
> use... I
> usually will give them that, but not much more.

I totally agree.  Skip schemtics entirely when doing FPGA designs.

My FPGA testbenches include bus-functional models of everything the  
FPGA talks to.  To support this, I use either vendor-supplied models  
(memories and such) or I write them myself.  (PLX wanted me to give  
them my Verilog models of their 9030 and 9656 chips, so my company  
said, "you'll need to pay us..." and that ended that discussion quite  
quickly.)  The microcontroller or whatever talks to the FPGA, which  
does something interesting, and interesting outputs result, which are  
compared to an expected result.

The automatic block diagram is interesting, if only to put on a slide  
for a design review, but I'd argue that you should have your block  
diagram draw BEFORE you start coding ...

-a


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