Re: gEDA-user: vhdl and gschem

[al davis <ad136@xxxxxxxxxxxxxxxx>]

On Friday 16 February 2007 17:48, Stuart Brorson wrote:
> That being said, I must say that using a schematic capture
> package to do Verilog or VHDL seems to defeat the purpose.

Actually, VHDL and Verilog are very good as netlist languages.  
For automated generation, either is adequate, and VHDL has some 
nice features that really helpful.  For manual entry, the 
Verilog format is clear, compact, and regular. .. far superior 
to the Spice format.  The next real release of gnucap will use 
Verilog as the default netlist language, and read Spice files 
through a plug-in.

When making a netlister, all symbols should be appropriately 
translated to the target format.  No exceptions.  This is easy 
to do with VHDL and Verilog, but extremely difficult to do in a 
useful way for Spice.

Another comment on gnucap ....  I  am thinking of having the 
simulator core include no models at all, not even a resistor.  
All models are attached as plugins.  There will be a 
development snapshot in a day or so that makes serious use of 
plugins, and probably 3 new plugin libraries, mostly models 
that you can attach as you want, without the baggage of the 
ones you don't.  By use of a simple wrapper, it will take Spice 
model code (.c files) as plugins with no changes required.  It 
will take 3f, 3e, or ngspice format.  That means it is now 
easier to install a Spice model in gnucap than it is to install 
it in Spice.  Commands are plugins too.  The only command that 
is really required to be built-in is "attach", but 
even "attach" can be replaced by a user, at run time.


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