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gEDA-user: gnucap segmentation fault
I am simulating a circuit that has an LM741 and I'm getting a segmentation fault. I suspect the problem may be because the symbol I'm using for the LM741 has two pin error. The symbol's pin attributes areIt so happens that these two pins are the two offset null pins. I don't see these pins in the symbol. See an excerpt of the netlist below and the gnetlist cammand output below that:
--------------------------------------------------------------------------------------------------------------
--- checking package = X1
device = IC
Found subcircuit. Refdes = X1
Model info not found in model file list. No model attribute either. Just write what we know.
Invalid wanted_pin passed to get-nets [unknown]
In write-net-names-on-component. . . .
pin-name = 1
pinnumber = unknown
pinseq = unknown
netname = ERROR_INVALID_PIN
For X1, found pin with no pinseq attribute. Ignoring. . . .
In write-net-names-on-component. . . .
pin-name = 2
pinnumber = 2
pinseq = 2
netname = bottomLeg
In write-net-names-on-component. . . .
pin-name = 3
pinnumber = 3
pinseq = 3
netname = topLeg
In write-net-names-on-component. . . .
pin-name = 4
pinnumber = 4
pinseq = 4
netname = -Vcc
Invalid wanted_pin passed to get-nets [unknown]
In write-net-names-on-component. . . .
pin-name = 5
pinnumber = unknown
pinseq = unknown
netname = ERROR_INVALID_PIN
For X1, found pin with no pinseq attribute. Ignoring. . . .
--- checking package = C2
--------------------------------------------------------------------------------------------------------------
Microphone switch
* gnetlist -v -g spice-sdb -o micnetlist.ckt micSwitch4Sim.sch
*********************************************************
* Spice file generated by gnetlist *
* spice-sdb version 4.28.2007 by SDB -- *
* provides advanced spice netlisting capability. *
* Documentation at http://www.brorson.com/gEDA/SPICE/ *
*********************************************************
*vvvvvvvv Included SPICE model from /home/rob/gaf/spice-files/LM741.subckt vvvvvvvv
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@xxxxxxxxxxxxxx
*//////////////////////////////////////////////////////////
*LM741 OPERATIONAL AMPLIFIER MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LM741 1 2 99 50 28
*
*Features:
*Improved performance over industry standards
*Plug-in replacement for LM709,LM201,MC1439,748
*Input and output overload protection
*
****************INPUT STAGE**************
*
IOS 2 1 20N
*^Input offset current
R1 1 3 250K
R2 3 2 250K
I1 4 50 100U
R3 5 99 517
R4 6 99 517
Q1 5 2 4 QX
Q2 6 7 4 QX
*Fp2=2.55 MHz
C4 5 6 60.3614P
*
***********COMMON MODE EFFECT***********
*
I2 99 50 1.6MA
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 1E-3 1
*Input offset voltage.^
R8 99 49 40K
R9 49 50 40K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 1.63
D1 9 8 DX
D2 10 9 DX
V3 10 50 1.63
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
G1 98 9 5 6 2.1E-3
*Fp1=5 Hz
R5 98 9 95.493MEG
C3 98 9 333.33P
*
***************POLE STAGE***************
*
*Fp=30 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 5.3052E-15
*
*********COMMON-MODE ZERO STAGE*********
*
*Fpcm=300 Hz
G4 98 16 3 49 3.1623E-8
L2 98 17 530.5M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 50 99 POLY(1) V6 450U 1
E1 99 23 99 15 1
R16 24 23 25
D5 26 24 DX
V6 26 22 0.65V
R17 23 25 25
D6 25 27 DX
V7 22 27 0.65V
V5 22 21 0.18V
D4 21 15 DX
V4 20 22 0.18V
D3 15 20 DX
L3 22 28 100P
RL3 22 28 100K
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL QX NPN(BF=625)
*
.ENDS
*$
*^^^^^^^^ End of included SPICE model from /home/rob/gaf/spice-files/LM741.subckt ^^^^^^^^
*
*============== Begin SPICE netlist of main design ============
V2 bottomLeg 0 dc 5
R5 0 bottomLeg 1k
R4 V2 1 10k
V1 topLeg bottomLeg ac 1
R3 bottomLeg topLeg 10k
.INCLUDE /home/rob/gaf/spice-files/LM741.subckt
R2 bottomLeg 0 100k
C4 -Vcc 0 .1u
X2 ecuMic 1 -Vcc LM741
R1 0 topLeg 100k
C3 Vcc 0 .1u
X1 bottomLeg topLeg -Vcc LM741
C2 -Vcc 0 .1u
C1 Vcc 0 .1u
R8 0 ecuMic 10k
R7 0 computerMic 10k
V3 V2 0 dc 5 ac 1
R6 bottomLeg computerMic 1k
.op
.print ac v(topLeg) v(bottomLeg) v(computerMic)
.ac lin 300 3000 5 >micsim.dat
.end
--------------------------------------------------------------------------------------------------------------
If I go into the symbol the pin/pin_seq attributes are as follows:
pinnumber pinseq
------------------------
2 2
3 3
4 4
6 6
7 7
Above it shows for component X1 these pin attributes:
pinnumber = unknown, pinseq = unknown and netname = ERROR_INVALID_PIN
Is this the cause of the segmentation fault? If so, there is no pin 1 or 5 in the symbol. How can I correct it?
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