Re: gEDA-user: Was there a major change to how power nets are handled in netlists?

[Ales Hvezda <ahvezda@xxxxxxxxxxxxxx>]

[snip]
>I will try making a smaller test case again, but haven't had luck so
>far.  I would feel better if I knew that you saw the problem in the
>netlist I sent.
>

	Okay, I am now able to reproduce the problem with the following
attached schematics.  I generally do not like to netlist schematics with
missing components, but in this case the problem does also occur in the
larger set you sent me.

	I ran gnetlist 20070526 (which is 1.0) and 1.4.3:

gnetlist -g geda one.sch two.sch
or 
gnetlist -g geda two.sch one.sch

	and produced the following output:

START components

R1 device=RESISTOR
C2 device=CAPACITOR
C1 device=CAPACITOR

END components

START renamed-nets

DVDD_FPGA -> Vcco2

END renamed-nets

START nets

Vcco3 : C2 1 
Vcco2 : R1 1, C1 1 

END nets

Depending on the order of the schematics on the gnetlist line, you will
get a different net renamed (DVDD_FPGA -> Vcco2 or DVDD_FPGA -> Vcco3).

This is most certainly a bug in gnetlist and probably has been there
since the beginning of time.  I am guessing it worked in the past due
to shear luck.  I haven't yet gone back further than 1.0, but I suspect
this has never worked right.

You have three choices in the short term:

	- Wait until I figure out how to fix this (no guarantees, but I 
	  really don't like netlister bugs like this)
	- Fix up your schematic to not connect multiple power symbols to 
	  the same net or name the same net multiple times across sheets
	- Post process your netlist to combine the nets which should be
	  connected together.


								-Ales

#text/plain [one.sch] /home/ahvezda/one.sch
#text/plain [two.sch] /home/ahvezda/two.sch



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