Re: gEDA-user: How to achive ~90us delay on a digital line

[gene <carzrgr8@xxxxxxxxxxxxx>]

> I was thinking of solutions, like a uC with UART, some big fifo, etc. 
> However if any of you have simpler solution, could you please share with me?
> 

This is just an off-the-cuff answer, without getting into the details of 
your design.  But what about an L-C or R-C delay plus a schmitt-trigger 
buffer?  Change the delay with L or C, or R or C.  The buffer will 
restore the signal shape and amplitude (i.e. square it up) Timing 
accuracy may suffer a little with part-to-part thresholds (on the 
buffer), but it's dirt cheap and very flexible.

If you happen to have a CPLD or FPGA around, build a shift register.

gene



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