Re: gEDA-user: how to make DRC ignore "outline" layer?

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Wed, 2010-02-10 at 23:16 +0000, Peter Clifton wrote:
> On Wed, 2010-02-10 at 16:22 -0600, Mark Rages wrote:
> > Hi, I'm making a layout with castellated vias on the edge.  so these
> > vias intersect the outline layer and pcb thinks they are all shorted
> > together when I press "o".
> > 
> > Any way around this?  I thought the magic was the name "outline".
> 
> Probably needs a kludge in src/find.c
> 
> Somewhere in LookupLOConnectionsToPVList() perhaps, where it loops over
> the layers and scans for connectivity to them. Also, check
> LookupPVConnectionsToLOList().
> 
> The magic test for an outline layer is:
> 
>   if (strcmp (Layer->Name, "outline") == 0)
>     continue;

Brownie points for a tested patch..
Bonus points for a patch which wraps the magic test in a new macro /
function, something like:

 if (!LAYER_IS_COPPER (Layer))
    continue;

To skip the connectivity tests for other non-copper layers.





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