Re: gEDA-user: analog/code co-simulation and schematics and netlists for silicon

[John Griessen <john@xxxxxxxxxxxxxx>]

al davis wrote:
> On Tuesday 23 February 2010, John Griessen wrote:
> > Would you still use gschem/gnetlist to schematically connect
> > verilog modules?  That depends on having a good translator
> >  first, right?
>
> Anything that generates a netlist.
>
> Gnucap uses "language plugins" to read whatever input format.  
> Maybe someone could make a language plugin to read and write the 
> gschem format directly.  Once this is done, it will also give us 
> a stand-alone translator, both ways, between any of the 
> supported formats.
>
> > Could you just use a top level schematic as a guide for
> >  connecting code modules to simulate with no netlist
> >  generated from gschem?
>
> Sure, but do you want to?

Only as a stopgap measure.  I can't dive into the translator project, but I've hinted
to Mr. Wender about it -- and it sounds very much aligned with their goals the more I
think about it.

John Griessen


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