Re: gEDA-user: any last minute advice prior to sending out for PCB fab

[Dan McMahill <dan@xxxxxxxxxxxx>]

gene glick wrote:
> After a very long time, I am just about ready to send out 3 different 
> boards for fab.  I would appreciate any advice to improve my chances of 
> success.  So far here's what has been done:
>
> 1. Run DRC on all PCBs with no issues..
> 2. Checked schematics.
> 3. Checked schematic matches layout.
> 4. In process of checking all the components, especially the transistor 
> pinouts (all SOT23 devices)
> 5. Checked the board dimensions. These boards plug into one another, so 
> have to be sure they match up.  It looks good physically and the pin 
> numbers look correct from board-to-board.
> 6. Checked the soldermask.  I found a bunch with very minimal dam 
> spacing so fixed them.
> 7. fixed cosmetic trace runs that looked ugly.
> 8. double checked for unused traces left behind from component moves.
>
>
> The cash layout for PCB fab is going to be large enough that I am 
> nervous about not getting it right.  Still, I have a CPU card and SMPS 
> to do which can wait a bit while this gets put together.
>
> what else?  Any suggestions?


don't even consider ordering boards without loading up the photoplot 
files into something like gerbv and doing some sanity checks.  This 
advice applies to a design done with any layout tool and not just pcb. 
A minimal list would be:

- From 20,000 feet, does each layer look right or are there glaring 
errors like a big missing chunk of a ground plane.

- On your plane layer(s), make sure that you see some pins/vias that go 
through the plane *without* connecting.  Now make sure you see some that 
*do* connect.  Yes, I have seen a case where someone (not me) ordered a 
board that had exactly 0 connections to the ground plane.  All thermals 
were missing. Didn't work so well.

- Mounting holes there?  In the right place?

- If you're using new footprints, especially high pin count QFN's, and 
QFP's where there are versions with different pin pitch for the same pin 
count, then do at least some sanity checks on pin pitch.  For example on 
a 128 pin TQFP, measure from pin 1 center to pin 32 center , divide by 
31 and make sure you get the right answer.

- On new leaded connector footprints, at least spot check your hole sizes.

- for the top and bottom layers, toggle on/off the associated soldermask 
relieve layer and see that it appears that your pads and pins are 
covered.  I don't usually check every single pad but at least do a high 
level check to see that it is about right.

- for the top and bottom layers, turn on the solder mask relief and 
toggle the silk screen layers and look for silk over pad openings.

--------------------------------------------

For these last 2 cases, I'd love to see a tool that used libgerbv that 
could do boolean operations on layers to compute things like:

  err_top_silk = layer_and(top_silk, top_soldermask_relief)

In other words something that could do an after the fact set of DRC 
checks.  But that is a whole other project.


-Dan





- Ma


_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user