Re: gEDA-user: PAL/CPLD programming

[Charles Lepple <clepple@xxxxxxxxx>]

On Tue, 11 Jan 2005 23:53:13 -0500, Dave McGuire <mcguire@xxxxxxxxxxxxx> wrote:
>    Well...the chips themselves don't seem to be going away.  Why not
> come up with some free tools?

"All" that is needed is for someone with a bit of C++ experience, and
knowledge of Quine-McClusky (sp?) to fix up Steve's ipal code. The
only part that it does not do is convert the netlist to
sum-of-products (or product-of-sums; I forget which the PALs implement
natively), and then fill in the fuse map with the combinational logic.
ipal takes care of writing the JEDEC file, allocating the registers,
etc.

I looked at this in depth a while back, but a) I'm not so good with
C++ and b) I don't quite understand the workings of QM well enough to
reimplement it in the framework of someone else's code.

One could try to reimplement PALASM, but I think you're faced with the
same logic minimization problems-- so you might as well start with
Verilog as the HDL, since the framework is already there.

-- 
- Charles Lepple