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Re: gEDA-user: Vias with zero clearance in PCB?

To: geda-user@xxxxxxxx
Subject: Re: gEDA-user: Vias with zero clearance in PCB?
From: DJ Delorie <dj@xxxxxxxxxxx>
Date: Mon, 9 Jan 2006 22:37:35 -0500
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References: <17702B6B8A6ED241BF737ACF8D432DA009A7F8@aplesjustice.dom1.jhuapl.edu> <200601100214.k0A2EZ2J024087@envy.delorie.com> <17702B6B8A6ED241BF737ACF8D432DA009A7F9@aplesjustice.dom1.jhuapl.edu>
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> So, are amazing little tidbits like this one written up somewhere in
> one place?

You mean, besides the source code?  That's where I had to look to find it.

Actually, I brought up the problem of forced clearance a while back.
IMHO we should have a flag for pins/vias that forces "no clearance".

But yeah, we know the docs are weak.  I'm in the middle of redoing the
GUI, maybe I'll work on the docs after that's finished.

Follow-Ups:
- gEDA-user: PCB doc on wiki (was RE: Vias with zero clearance in PCB?)
  - From: Jose, Marshall

References:
- gEDA-user: Vias with zero clearance in PCB?
  - From: Jose, Marshall
- Re: gEDA-user: Vias with zero clearance in PCB?
  - From: DJ Delorie
- RE: gEDA-user: Vias with zero clearance in PCB?
  - From: Jose, Marshall

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