Re: gEDA-user: Test pads in PCB

[Dan McMahill <dan@xxxxxxxxxxxx>]

Stuart Brorson wrote:
> Putting testpadding directly into PCB is a little tricker since PCB
> needs to know that the testpad is a non-netlist structure which
> shouldn't cause DRCs by itself (but should be checked for shorts to
> other nets, just like a polygon region or a via).  One way to do it is
> to make a testpad a differentt type of via -- just like a non-plated
> through-hole is a different type of via.  That is, you place a
> testpad, then click on it to edit its properties:  Select "testpad",
> and it turs off the drill hole, and puts a metal disk on only the top
> (or bottom) layer.

I disagree.  I think testpads _are_ a netlist structure.  After all you 
care about the connectivity.  What I'm thinking of is an action which 
adds a test pad to each net in the connectivity database and 
instantiates test pads.  Perhaps there should be a mode where you can 
simply start placing test pads by clicking and as you do so they are 
added to the netlist.  Then have a some manufacturing rule check which 
verifies that you have a testpad on every net.

-Dan