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gEDA-user: Re: hierarchy of schematics



On Wed, 03 Jan 2007 22:27:16 -0700, Andy Peters wrote:

> On Dec 20, 2006, at 8:34 AM, John Griessen wrote:
>> We need to dream one up, a gschem schematic to sub-schematic-symbol  
>> genreating script, that is....
> 
> Agreed, this is necessary for board designs (I won't do an FPGA  
> design in a schematic).  It's impossible to get even a small design  
> to fit onto one B-size sheet, considering how things are scaled in  
> gschem.  (My little IR volume control design is three sub-sheets plus  
> a top level.)
> 
> I haven't sorted out exactly how (or even IF) gsch2pcb sorts things  
> out when a project has more than one page and no top-level sheet with  
> lower-level sheet symbols.  My guess is that all net names are  
> global, and in-1.sym and out-1.sym (for example) are purely  
> informational.  I also don't know if the DRC is smart enough to tell  
> you if an output on sheet A is connected to an output on sheet B.

Just tested this the other day for a set trivial sub sheets. 
Result: Pin names and components receive the refdes of the top level
symbol as a prefix. Thus they are strictly local to the sub sheet. It is
even possible to source the same sub sheet several times in the master
sheet. 
The port symbols in-1.sym and out-1.sym are not quite informal. The
important part is their refdes. The netlister gsch2pcb checks for every
pin label of the top level symbol if there is a refdes with the same name.
The drc2 output will issue a warning, if there is a pin in the top level
symbol that corresponds to no port on the sub sheet. It will also warn if
a port symbol does not connect to a pin in the top level symbol. 


> Some mechanism to automatically generate a "sheet symbol" would be very  
> useful.

Ack. This is, what John G. was talking about. 

---<(kaimartin)>---
(I will netlist my first big sub sheet project today after the unconnected
pin errors have been dealt with...)
-- 
Kai-Martin Knaak
http://lilalaser.de/blog



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