On 01/19/2011 06:23 PM, Markus Hitter wrote:
One possible drawback for both ideas: you can't route tracks through the "foreign" area/sub-layout, even if there's enough room after assembling the zones.
In chip layout, where you do have layout sub-cells definable by the tools, all you do for for the route through tracks is put them in the sub-cell as a floating unconnected trace that you do LVS on only at a higher level of completeness -- when it's with the surroundings. Floating tracks might trigger a DRC, but I think they are perfectly valid and I'd rewrite the DRC. I can't remember if DRC2 or anything else complains about floating tracks... John -- Ecosensory Austin TX _______________________________________________ geda-user mailing list geda-user@xxxxxxxxxxxxxx http://www.seul.org/cgi-bin/mailman/listinfo/geda-user