Re: gEDA-user: gaf and verilog?

["Mike Jarabek" <mjarabek@istop.com>]

mcmahill@mtl.mit.edu said:

> 
> that change might be nice.

I have to upgrade my build environment to the latest autoconf and friends. (I
haven't been keeping up with Ales...)  In the meantime, you can add the
attribute `VERILOG_PORTS=POSITIONAL' to the chips on your design.  This will
cause the netlister to avoid outputting named port declarations.  You can then
create models for the 74xx chips that you are using, naming the ports in the
right order.
 
> What is the primary purpose of the verilog backend for gnetlist then?  Is
> it pretty much only for users doing gate level modeling with parts from 
> the 'verilog' library?

I originally envisioned it to be used to create toplevel schematics for FPGA's
and ASICs.  The gates are provided for that little bit of logic that might be
needed between blocks, if it helps for clarity.  The netlister gladly creates
sub blocks from symbols generated by gmk_sym that represent verilog modules.
This first purpose should not prohibit board level simulation though.

>  On a related note, I played around with it and
> couldn't figure out how to make the module definition.  Ie, what do I
> instantiate in the schematic to end up with a module name and port list?

From gnetlist/docs/README.verilog:
---------
	   4) Insert IPAD's, OPAD's, and IOPAD's for all the nets you
              want to be visible in the module declaration statement.
              It is especially important to make sure that the nets
              you hook up to the pads are named, as the net names
              could change from run to run, that's a bad thing. (I/O
              pads would be a good place to put the aformentionned
              full range expressions.  Range expressions on I/O pads
              are ignored when outputting the module declaration, but
              they are used in figuring out the final bit ranges.)
              Every pad must have a unique uref, otherwise the
              netlister will get confused.

 	   5) Add an unattached attribute `module_name=Your_Module'
	      somewhere on the schematic, near the title block is
	      good.  This will name the generated Verilog module
	      `Your_Module'.
----------

Use the symbols from the Verilog library to do this.  You may need to edit the
system-rc files to ensure that the Verilog primitives are picked up before the
VHDL ones.

Have fun!

-- 
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                              Mike Jarabek
                                FPGA/ASIC Designer
   http://www.doncaster.on.ca/~mjarabek
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