Re: gEDA-user: OT: (Vhdl help)

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Thu, 2008-06-26 at 15:50 -0700, Larry Doolittle wrote:
> On Thu, Jun 26, 2008 at 02:56:22PM -0700, Ben Jackson wrote:
> > On Thu, Jun 26, 2008 at 07:47:57PM +0100, Peter Clifton wrote:
> > In the case of I2C where you only want inputs and pulldowns, 'O' is always
> > 0 (zero) and T should be true when you want to pull down.  My own i2c
> > module has inputs sda, scl and outputs sda_pull and scl_pull.  At the top
> > level they're connected like:
> > 
> > 	assign SDA_PIN = sda_pull ? 0 : 1'bZ;
> > 	assign sda = SDA_PIN;
> 
> I have lots of practice writing and using serial communication
> in Xilinx, including what I believe is I2C for a TCN75.  Even
> though it's Verilog, I'll attach a working (production) module
> that gateways SPI and I2C devices to a non-real-time computer.
> 
> And yes, buried in there you will see the line
> assign SDA75 = tcn_drive ? 1'bz : 1'b0 ;
> 
>   - Larry

Thanks for the example.

I've yet to decide whether this will be built with an I2C module which
interfaces on a data + address-bus, then synthesise a soft-core to do my
housekeeping processing.

The tasks on the I2C are interfacing various statuses and commands with
a an external PLC, temperature monitoring, polling configuration
DIP-switches.

We'll do all the PWM generation / time-critical hardware in VHDL, but it
seems that C is a more intuitive language to do the control logic than
writing lots of large state-machines.

Unfortunately, my main concern at the moment is the FPGA module
(designed to drop in and replace obsolete through-hole logic), doesn't
seem to be able to manage a fast clock signal for the ADCs.. 10Mhz looks
like a pathetic attempt at a triangle wave. 4Mhz is not a great deal
better, although appears to be exciting the ADCs OK.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)



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